Stacked semiconductor package and method for manufacturing the same

ABSTRACT

A stacked semiconductor package includes a semiconductor package module including a plurality of semiconductor packages each of which has a first surface, a second surface facing away from the first surface, side surfaces connecting the first surface and the second surface and through-holes formed on the side surfaces to pass through the first surface and the second surface and which are stacked such that their through-holes vertically connect with one another, and adhesive members which are formed between the semiconductor packages and attach the semiconductor packages to one another, a main substrate supporting the semiconductor package module and formed, on a third surface thereof facing the semiconductor package module, with main connection pads which are aligned with the through-holes, and conductive connection members formed in the through-holes and electrically connecting the semiconductor packages with the main connection pads.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority to Korean patent applicationnumber 10-2010-0042457 filed on May 6, 2010, which is incorporatedherein by reference in its entirety.

BACKGROUND OF THE INVENTION

The present invention relates to a stacked semiconductor package and amethod for manufacturing the same.

In the semiconductor industry, packaging technologies for semiconductorintegrated circuits have continuously are being developed to meet thedemands toward miniaturization and mounting efficiency. For example, thedemand for miniaturization is accelerating the development oftechnologies for a package having a size approaching to that of a chip,and the demand for mounting reliability is highlighting the importanceof packaging technologies for improving the efficiency of mounting workand mechanical and electrical reliability after mounting. Also, asminiaturization and high performance are demanded in electric andelectronic products, stacking technologies have been suggested in theart and are currently being developed into various styles.

The term “stack” referred to in the semiconductor industry means atechnology of vertically piling at least two semiconductor chips orsemiconductor packages. By using the stack technology, for example, a512M DRAM may be configured by stacking two 256M DRAMs. Further, since astacked semiconductor package provides advantages in terms of memorycapacity, mounting density and mounting area utilization efficiency,search and development of stacked semiconductor packages are beingaccelerated.

FIG. 1 is a cross-sectional view illustrating a known POP (Package OnPackage) type stacked semiconductor package. A lower package 20 and anupper package 30 are stacked on a main substrate 10 while electricallyconnected by solder balls 41 and 42.

In detail, the main substrate 10 and the lower package 20 areelectrically connected with each other by the solder balls 41 which areformed between ball land patterns 11 formed on the upper surface of themain substrate 10 and ball land patterns 23A formed on the lower surfaceof a substrate 21 of the lower package 20, and the lower package 20 andthe upper package 30 are electrically connected with each other by thesolder balls 42 which are formed between ball land patterns 23B formedon the upper surface of the substrate 21 of the lower package 20 andball land patterns 33 formed on the lower surface of a substrate 31 ofthe upper package 30.

The unexplained reference numerals 22, 24, 25 and 26 respectivelydesignate a first semiconductor chip, a first adhesive member, firstbonding wires and a lower mold part which constitute the lower package20, and the unexplained reference numerals 32, 34, 35 and 36respectively designate a second semiconductor chip, a second adhesivemember, second bonding wires and an upper mold part which constitute theupper package 30.

However, in the known stacked semiconductor package, warpage may occurin the main substrate 10, the lower package 20 and the upper package 30when performing a reflow process for the solder balls 41 and 42, and dueto the occurrence of warpage, cracks may occur in the solder balls 41and 42. The occurrence of cracks may lead to the occurrence of fails,whereby the manufacturing yield and the productivity may deteriorate.

BRIEF SUMMARY OF THE INVENTION

Embodiments of the present invention are directed to a stackedsemiconductor package and a method for manufacturing the same which cansuppress the occurrence of a fail.

In an exemplary embodiment of the present invention, a stackedsemiconductor package includes a semiconductor package module includinga plurality of semiconductor packages each of which has a first surface,a second surface facing away from the first surface, side surfacesconnecting the first surface and the second surface and through-holesformed on the side surfaces to pass through the first surface and thesecond surface and which are stacked such that their through-holesvertically connect with one another, and adhesive members which areformed between the semiconductor packages and attach the semiconductorpackages to one another, a main substrate supporting the semiconductorpackage module and formed, on a third surface thereof facing thesemiconductor package module, with main connection pads which arealigned with the through-holes, and conductive connection members formedin the through-holes and electrically connecting the semiconductorpackages with the main connection pads.

In another exemplary embodiment of the present invention, a method formanufacturing a stacked semiconductor package includes the steps offorming a plurality of semiconductor packages each having a firstsurface, a second surface facing away from the first surface and sidesurfaces connecting the first surface and the second surface, andformed, on the side surfaces, with through-holes which pass through thefirst surface and the second surface, attaching first adhesive membersto second surfaces of the semiconductor packages in such a way as topartially cover cross-sections of through-holes which are open on thesecond surfaces of the semiconductor packages, inserting solder ballsinto the through-holes, stacking the semiconductor packages on a mainsubstrate formed with main connection pads such that the through-holesof the semiconductor packages vertically connect with one another, andreflowing the solder balls and thereby forming conductive connectionmembers which electrically connect the semiconductor packages with themain connection pads.

In another exemplary embodiment of the present invention, a stackedsemiconductor package includes a plurality of semiconductor packagemodules each including a plurality of semiconductor packages each ofwhich has a first surface, a second surface facing away from the firstsurface, side surfaces connecting the first surface and the secondsurface and through-holes formed on the side surfaces to pass throughthe first surface and the second surface and which are stacked such thattheir through-holes vertically connect with one another and adhesivemembers which are formed between the semiconductor packages and attachthe semiconductor packages to one another, and formed adjoining oneanother in a matrix type such that through-holes of the semiconductorpackages, which connect in a vertical direction, connect in a horizontaldirection, a main substrate supporting the semiconductor package modulesand formed, on a third surface thereof facing the semiconductor packagemodules, with main connection pads which are aligned with thethrough-holes communicating in the vertical direction; and conductiveconnection members formed in the through-holes and electricallyconnecting the semiconductor packages with the main connection pads.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view illustrating a known POP type stackedsemiconductor package.

FIG. 2 is a perspective view illustrating a stacked semiconductorpackage in accordance with an exemplary embodiment of the presentinvention.

FIG. 3 is a cross-sectional view taken along the line I-I′ of FIG. 2.

FIG. 4 is a partially broken-away perspective view of the semiconductorpackage shown in FIG. 2.

FIGS. 5 through 12 are views explaining a method for manufacturing thestacked semiconductor package shown in FIG. 2.

FIG. 13 is a perspective view illustrating a stacked semiconductorpackage in accordance with another exemplary embodiment of the presentinvention.

FIG. 14 is a cross-sectional view taken along the line II-II′ of FIG.13.

FIGS. 15A and 15B are views explaining effects achieved in the stackedsemiconductor package in accordance with another exemplary embodiment ofthe present invention.

DESCRIPTION OF SPECIFIC EMBODIMENTS

Hereafter, specific embodiments of the present invention will bedescribed in detail with reference to the accompanying drawings.

It is to be understood herein that the drawings are not necessarily toscale and in some instances proportions may have been exaggerated inorder to more clearly depict certain features of the invention.

FIG. 2 is a perspective view illustrating a stacked semiconductorpackage in accordance with an exemplary embodiment of the presentinvention, FIG. 3 is a cross-sectional view taken along the line I-I′ ofFIG. 2, and FIG. 4 is a partially broken-away perspective view of thesemiconductor package shown in FIG. 2.

Referring to FIGS. 2 and 3, a stacked semiconductor package inaccordance with an exemplary embodiment of the present inventionincludes a semiconductor package module 40, a main substrate 50, andconductive connection members 60.

The semiconductor package module 40 includes a plurality ofsemiconductor packages 100 and first adhesive members 200. In thepresent exemplary embodiment, the semiconductor package module 40includes three semiconductor packages 100.

Referring to FIG. 4, each semiconductor package 100 has a first surface100A, a second surface 100B which faces away from the first surface100A, and side surfaces 100C which connect the first surface 100A andthe second surface 1006. In the present exemplary embodiment, eachsemiconductor package 100 has a rectangular hexahedral shape. Thesemiconductor package 100 having a rectangular hexahedral shape has fourside surfaces 100C. Through-holes 140 are formed on the side surfaces100C of the semiconductor package 100 in such a way as to pass throughthe first surface 100A and the second surface 100B. In the presentexemplary embodiment, the through-holes 140 are formed in a pluralnumber on the side surfaces 100C of the semiconductor package 100. Eachof the through-holes 140 may have a shape of a circular column.

According to an example, an inner diameter D of the through-holes 140has a size that is larger than the diameter of solder balls, so that thesolder balls can be inserted into the through-holes 140. Also, in orderto prevent the inserted solder balls from moving out of thethrough-holes 140, an open width W of the through-holes 140, by whichthe through-holes 140 are open on the side surfaces 100C of thesemiconductor package 100, has a size that is smaller than the diameterof the solder balls and the inner diameter D of the through-holes 140.For example, the open width W of the through-holes 140 may beapproximately 10% to 50% of the inner diameter D of the through-holes140. While the through-holes 140 have the shape of a circular column inthe present exemplary embodiment, the through-holes 140 may have a shapeof a prism with at least three sides.

In the present exemplary embodiment, the semiconductor package 100includes a substrate 110 and a mold part 130 through which thethrough-holes 140 are formed, and a semiconductor chip 120.

According to an example, the substrate 110 has a shape of a quadrangularplate. The substrate 110 has a fifth surface 110A, a sixth surface 110Bwhich faces away from the fifth surface 110A, and four side surfaces110C which connect the fifth surface 110A and the sixth surface 110B.

Connection pads 112 are formed on the fifth surface 110A of thesubstrate 110, and side pads 113 are formed on the inner walls of thethrough-holes 140 formed on the side surfaces 110C of the substrate 110.While not shown in a drawing, the substrate 110 may include thereincircuit patterns (not shown) which are formed to constitute multiplelayers and vias (not shown) which electrically connect the circuitpatterns formed on different layers. The connection pads 112 and theside pads 113 may be electrically connected with each other through thecircuit patterns and vias which are formed in the substrate 110.

The semiconductor chip 120 has a seventh surface 121 which faces thesubstrate 110 and an eighth surface 122 which faces away from theseventh surface 121.

The seventh surface 121 of the semiconductor chip 120 is attached to thefifth surface 110A of the substrate 110 with a second adhesive member150, and bonding pads 123, which are connected with the connection pads112 of the substrate 110, are formed on the eighth surface 122 of thesemiconductor chip 120. While not shown in a drawing, a circuit unit(not shown), which is constituted by transistors, capacitors, resistors,and so forth to store and process data, is formed in the semiconductorchip 120, and the bonding pads 123 serve as electrical contacts of thecircuit unit, for connection to an outside.

In the present exemplary embodiment, the connection pads 112 of thesubstrate 110 and the bonding pads 123 of the semiconductor chip 120 areconnected with each other by bonding wires 124. While, in the presentexemplary embodiment, the substrate 110 and the semiconductor chip 120are connected with each other in a wire bonding type by using thebonding wires 124, the substrate 110 and the semiconductor chip 120 maybe connected with each other in a flip-chip bonding type.

The mold part 130 seals the fifth surface 110A of the substrate 110including the semiconductor chip 120 and the bonding wires 124.

Referring back to FIGS. 2 and 3, the plurality of semiconductor packages100 are stacked such that the through-holes 140 are vertically alignedwith one another, and thereby, 7 constitute the semiconductor packagemodule 40.

The first adhesive members 200 are formed between the stackedsemiconductor packages 100. Each first adhesive member 200 attaches thesecond surface 100B of an upwardly positioned semiconductor package 100and the first surface 100A of a downwardly positioned semiconductorpackage 100 to each other.

The first adhesive members 200 are formed in such a way as to partiallycover the cross-sections of the through-holes 140 which are open on thefirst surfaces 100A and the second surfaces 100B of the semiconductorpackages 100. For example, the first adhesive members 200 are formed tocover approximately 20% to 50% of the cross-sections of thethrough-holes 140. The first adhesive members 200 function to supportthe solder balls inserted into the through-holes 140 so as to preventthe solder balls from moving out of the through-holes 140.

The first adhesive members 200 may be formed as flexible adhesivesheets. As the adhesive sheets, for example, a WBL (wafer backsidelamination) film, a spacer tape, and a prepreg may be used.

The main substrate 50 supports the semiconductor package module 40.

The semiconductor package module 40 is attached to the main substrate 50with the first adhesive member 200 which is attached to the secondsurface 100B of the semiconductor package 100 positioned lowermost.

The main substrate 50 has a third surface 51 which faces thesemiconductor package module 40 and a fourth surface 52 which faces awayfrom the third surface 51. Main connection pads 53 are formed on thethird surface 51 of the main substrate 50 in such a way as to be alignedwith the through-holes 140.

The conductive connection members 60 are formed in the through-holes 140which electrically connect the stacked semiconductor packages 100 withthe main connection pads 53 of the main substrate 50. In the presentexemplary embodiment, the conductive connection members 60 electricallyconnect the side pads 113 which are formed on the side surfaces 110C ofthe substrates 110 of the stacked semiconductor packages 100 with themain connection pads 53 of the main substrate 50.

The conductive connection members 60 may be formed by verticallystacking the semiconductor packages 100, with the solder balls insertedinto the through-holes 140, on the third surface 51 of the mainsubstrate 50 and by melting the solder balls through a reflow process.

While not shown in a drawing, in the case of a semiconductor package 100which should be electrically isolated from the conductive connectionmembers 60, insulation balls may be inserted, instead of the solderballs, into the through-holes 140 which are formed in the correspondingsemiconductor package 100 such that the side pads 113 formed on the sidesurfaces 110C of the substrate 110 of the corresponding semiconductorpackage 100 are electrically isolated from the conductive connectionmembers 60. Here, silica balls may be used as the insulation balls.

A method for manufacturing the stacked semiconductor package having theabove-mentioned construction will be described below.

FIGS. 5 through 12 are views explaining a method for manufacturing thestacked semiconductor package in accordance with the above-describedexemplary embodiment of the present invention.

FIGS. 5, 7, 9, 11 and 12 are cross-sectional views according to aprocessing sequence, and FIGS. 6, 8 and 10 are plan views of FIGS. 5, 7and 9. For the sake of easy understanding, mold parts 130 are not shownin FIGS. 6, 8 and 10.

Referring to FIGS. 5 and 6, a strip level substrate 70, having aplurality of unit level substrates 110 each of which has a fifth surface110A and a sixth surface 110B facing away from the fifth surface 110Aand is formed with connection pads 112 on the fifth surface 110A thereofand with conductive layers 113A for side pads on the side surfacesthereof, is prepared.

Adjoining unit level substrates 110 are connected to each other along asawing line S, and the conductive layers 113A for side pads, of theadjoining unit level substrates 110, are coupled with each other.

While not shown in a drawing, each unit level substrate 110 may includetherein circuit patterns (not shown) which are formed to constitutemultiple layers and vias (not shown) which electrically connect thecircuit patterns formed on different layers. The connection pads 112 andthe conductive layers 113A for side pads may be electrically connectedwith each other through the circuit patterns and vias which are formedin the unit level substrate 110.

A semiconductor chip 120 is attached onto each unit level substrate 110with a second adhesive member 150, and bonding pads 123 of thesemiconductor chip 120 and the connection pads 112 of the unit levelsubstrate 110 are connected with each other by the bonding wires 124.

By forming a mold part 130 which seals the fifth surfaces 110A of theunit level substrates 110 including the bonding wires 124 and thesemiconductor chips 120, a plurality of strip level semiconductorpackages 100 are formed.

Referring to FIGS. 7 and 8, through-holes 140 are formed through thestrip level substrate 70 and the mold part 130 to pass through theconductive layers 113A for side pads, of the unit level substrates 110.The through-holes 140 may be formed through a drilling process or alaser drilling process.

An open width W of the through-holes 140 by which the through-holes 140are open on the side surfaces of the unit level substrates 110 isdetermined to have a size that is smaller than an inner diameter D ofthe through-holes 140 and the diameter of solder balls which are to beinserted into the through-holes 140. The conductive layers 113A for sidepads are not completely removed and remain in the through-holes 140. Bythe conductive layers 113A for side pads which remain in this way, sidepads 113 are formed on the inner walls of the through-holes 140 of theunit level substrates 110.

While the through-holes 140 formed in the unit level substrate 110 havethe substantial shape of a circular column in the present exemplaryembodiment, the through-holes 140 may have a shape of a prism with atleast three sides.

Referring to FIGS. 9 and 10, by cutting the strip level substrate 70 andthe mold part 130 along the sawing line S, the semiconductor packages100 are individualized.

Referring to FIG. 11, a first adhesive member 200 is attached to asurface of the individualized semiconductor package 100. Hereafter, thesurface of the semiconductor package 100, to which the first adhesivemember 200 is attached, is formed as a second surface 100B, and theother surface of the semiconductor package 100, which faces away fromthe second surface 100B, is formed as a first surface 100A.

The first adhesive member 200 is formed in such a way as to partiallycover the cross-sections of the through-holes 140 which are open on thesecond surface 100B of the semiconductor package 100. For example, thefirst adhesive member 200 is formed to cover approximately 20% to 50% ofthe cross-sections of the through-holes 140 which are open on the secondsurface 100B of the semiconductor package 100.

The first adhesive member 200 may be formed as a flexible adhesivesheet. As the adhesive sheet, for example, a WBL (wafer backsidelamination) film, a spacer tape, and a prepreg may be used.

Solder balls 300 are inserted into the through-holes 140. The solderballs 300, which are inserted into the through-holes 140, are supportedby the first adhesive member 200 and do not move downward out of thethrough-holes 140. Since the open width W of the through-holes 140 bywhich the through-holes 140 are open on the side surfaces of thesemiconductor package 100 is determined to have a size that is smallerthan the diameter of solder balls 300, the solder balls 300 insertedinto the through-holes 140 do not move sideward, as well, out of thethrough-holes 140, and remain inserted into the through-holes 140.

While not shown in a drawing, insulation balls are inserted, instead ofthe solder balls 300, into the through-holes 140 formed on the sidesurfaces of the semiconductor package 100 which need not be electricallyconnected. Here, silica balls may be used as the insulation balls.

Referring to FIG. 12, the semiconductor packages 100 are stacked on athird surface 51 of a main substrate 50 on which main connection pads 53are formed in such a manner that the through-holes 140 are verticallyaligned with the main connection pads 53. The semiconductor packages 100are vertically stacked on and attached to one another with firstadhesive members 200 which are formed on second surfaces 100B of thesemiconductor packages 100, and are attached to the main substrate 50with the first adhesive member 200 which is attached to thesemiconductor package 100 positioned lowermost.

Referring back to FIGS. 2 and 3, by melting the solder balls 300 througha reflow process, conductive connection members 60 are formed in such away as to electrically connect the side pads 113 formed in thesubstrates 110 of the semiconductor packages 100 with the mainconnection pads 53.

As the solder balls 300 are melted and flow downward during the reflowprocess, the conductive connection members 60 may not be formed in thethrough-holes 140 of upwardly stacked semiconductor packages 100. Inthis case, solder balls 300 are additionally inserted into thethrough-holes 140 after performing the reflow process, and the reflowprocess is performed again.

While it was described in the above exemplary embodiment that the solderballs 300 inserted into the through-holes 140 of the plurality ofsemiconductor packages 100 are melted at a time by performing the reflowprocess after stacking the plurality of semiconductor packages 100 onthe main substrate 50, the reflow process may be performed at each timeof stacking each semiconductor package 100 so that the solder balls 300can be melted by a semiconductor package 100.

FIG. 13 is a perspective view illustrating a stacked semiconductorpackage in accordance with another exemplary embodiment of the presentinvention, and FIG. 14 is a cross-sectional view taken along the lineII-II′ of FIG. 13.

Referring to FIGS. 13 and 14, a stacked semiconductor package inaccordance with another exemplary embodiment of the present inventionincludes a plurality of semiconductor package modules 40A, 40B, 40C and40D, a main substrate 50, and conductive connection members 60.

In the present exemplary embodiment, the stacked semiconductor packageincludes four semiconductor package modules 40A, 40B, 40C and 40D. Thefour semiconductor package modules 40A, 40B, 40C and 40D arerespectively formed as first through fourth semiconductor packagemodules, and hereafter, explanations will be made using these terms.

The first through fourth semiconductor package modules 40A, 40B, 40C and40D are formed on the main substrate 50 in a 2×2 matrix type such thatthe sides of the first through fourth semiconductor package modules 40A,40B, 40C and 40D contact with one another. That is to say, the secondsemiconductor package module 40B is formed neighboring the firstsemiconductor package module 40A in a first direction, and the thirdsemiconductor package module 40C is formed neighboring the firstsemiconductor package module 40A in a second direction perpendicular tothe first direction. The fourth semiconductor package module 40D isformed neighboring the first semiconductor package module 40A in adiagonal direction.

The first through fourth semiconductor package modules 40A, 40B, 40C and40D may have the same configuration as the semiconductor packagedescribed above in the first exemplary embodiment. Accordingly, repeateddescriptions for the same structures will be omitted herein, and thesame technical terms and the same reference numerals will be used torefer to the same component elements.

Each of the first through fourth semiconductor package modules 40A, 40B,40C and 40D has a structure in which semiconductor packages 100 formedwith through-holes 140 on respective side surfaces thereof arevertically stacked such that their through-holes 140 connect with oneanother.

The first through fourth semiconductor package modules 40A, 40B, 40C and40D are formed adjoining one another such that the through-holes 140vertically connecting with one another also connect with one another ina horizontal direction.

The main substrate 50 supports the first through fourth semiconductorpackage modules 40A, 40B, 40C and 40D.

The first through fourth semiconductor package modules 40A, 40B, 40C and40D are attached to the main substrate 50 with first adhesive members200 attached to second surfaces 100B of semiconductor packages 100positioned lowermost.

The main substrate 50 has a third surface 51 which faces the firstthrough fourth semiconductor package modules 40A, 40B, 40C and 40D and afourth surface 52 which faces away from the third surface 51. Mainconnection pads 53, which are aligned with the through-holes 140 of thefirst through fourth semiconductor package modules 40A, 40B, 40C and40D, are formed on the third surface 51 of the main substrate 50.

The conductive connection members 60 are formed in the through-holes 140of the first through fourth semiconductor package modules 40A, 40B, 40Cand 40D, and electrically connect side pads 113 which are formed insubstrates 110 of the semiconductor packages 100 included in the firstthrough fourth semiconductor package modules 40A, 40B, 40C and 40D, withthe main connection pads 53 of the main substrate 50.

The conductive connection members 60 are formed by mounting anddisposing the semiconductor packages 100 in the vertical and horizontaldirections with solder balls inserted into the through-holes 140 andperforming a reflow process to melt the solder balls.

While not shown in a drawing, in the case of a semiconductor package 100which should be electrically isolated from the conductive connectionmembers 60, insulation balls may be inserted, instead of the solderballs, into the through-holes 140 which are formed in the substrate 110of the corresponding semiconductor package 100 such that the side pads113 formed in the substrate 110 of the corresponding semiconductorpackage 100 may be electrically isolated from the conductive connectionmembers 60. Silica balls may be used as the insulation balls.

The through-holes 140, which are formed on the side surfaces of thefirst through fourth semiconductor package modules 40A, 40B, 40C and40D, connect with one another in the horizontal direction. Since thefirst through fourth semiconductor package modules 40A, 40B, 40C and 40Dare connected with the main substrate 50 by the conductive connectionmembers 60 which are formed in the through-holes 140, the number of themain connection pads 53 necessary for the main substrate 50 and thenumber of circuit wiring lines may decrease compared to the known art.

That is to say, in the case where the four semiconductor package modules40A, 40B, 40C and 40D are separately mounted onto the main substrate 50as shown in FIG. 15A, the number of circuit wiring lines needed in themain substrate 50 is 16 (=4×4). However, in the case where the foursemiconductor package modules 40A, 40B, 40C and 40D are adjacentlyformed in a 2×2 matrix type such that the through-holes 140 connect withone another in the horizontal direction as shown in FIG. 15B, the numberof circuit wiring lines needed in the main substrate 50 is only 6.

As is apparent from the above description, in the present invention,since stacked semiconductor packages are completely attached to oneanother with adhesive members, the occurrence of warpage in thesemiconductor packages may be suppressed. Also, because the stressesinduced due to warpage of the semiconductor packages may be alleviatedby the adhesive members which have flexibility, the occurrence of cracksin solder balls which are to be used as connection members may besuppressed. Further, since the solder balls which are used as theconnection members are formed on the side surfaces of the semiconductorpackages, the height of a stacked semiconductor package may decrease.Moreover, due to the fact that a semiconductor package module isconnected with an adjacent semiconductor package module through theconnection members, the number of circuit wiring lines needed in a mainsubstrate may decrease.

Although specific exemplary embodiments of the present invention havebeen described for illustrative purposes, those skilled in the art willappreciate that various modifications, additions and substitutions arepossible, without departing from the scope and the spirit of theinvention as disclosed in the accompanying claims.

What is claimed is:
 1. A stacked semiconductor package comprising: aplurality of semiconductor package modules each including a plurality ofsemiconductor packages each of which has a first surface, a secondsurface facing away from the first surface, side surfaces connecting thefirst surface and the second surface and through-holes formed on theside surfaces to pass through the first surface and the second surfaceand which are stacked such that their through-holes vertically connectwith one another and adhesive members which are formed between thesemiconductor packages and attach the semiconductor packages to oneanother, and formed adjoining one another in a matrix type such thatthrough-holes of the semiconductor packages, which connect in a verticaldirection, connect in a horizontal direction; a main substratesupporting the semiconductor package modules and formed, on a thirdsurface thereof facing the semiconductor package modules, with mainconnection pads which are aligned with the through-holes communicatingin the vertical direction; and conductive connection members formed inthe through-holes and electrically connecting the semiconductor packageswith the main connection pads.
 2. The stacked semiconductor packageaccording to claim 1, wherein each of the semiconductor packagescomprises: a substrate having a fifth surface, a sixth surface facingaway from the fifth surface and sides surfaces connecting the fifthsurface and the sixth surface, formed with connection pads on the fifthsurface, and formed with the through-holes on the side surfaces; asemiconductor chip placed on the substrate and having bonding pads whichare connected with the connection pads; and a mold part sealing thefifth surface of the substrate including the semiconductor chip andformed with the through-holes on side surfaces thereof.
 3. The stackedsemiconductor package according to claim 1, wherein the substrateincludes side pads which are formed on inner walls of the through-holesformed on the side surfaces of the substrate.
 4. The stackedsemiconductor package according to claim 1, wherein the through-holeshave the shape of a circular column or a prism with at least threesides.
 5. The stacked semiconductor package according to claim 1,wherein an open width of the through-holes, by which the through-holesare open on the side surfaces of the semiconductor package, has a sizethat is smaller than an inner diameter of the through-holes.
 6. Thestacked semiconductor package according to claim 5, wherein the openwidth of the through-holes has a size that corresponds to approximately10% to 50% of the inner diameter of the through-holes.
 7. The stackedsemiconductor package according to claim 1, wherein the adhesive membersare formed as flexible adhesive sheets.
 8. The stacked semiconductorpackage according to claim 7, wherein the adhesive members are formedusing any one of a WBL (wafer backside lamination) film, a spacer tape,and a prepreg.
 9. The stacked semiconductor package according to claim1, wherein the adhesive members are formed to partially covercross-sections of the through-holes which are open on the first surfaceand the second surface of the semiconductor packages.
 10. The stackedsemiconductor package according to claim 9, wherein the adhesive membersare formed to cover approximately 20% to 50% of the cross-sections ofthe through-holes.
 11. The stacked semiconductor package according toclaim 1, wherein the conductive connection members are formed usingsolder balls.